The present invention relates to a nonvolatile, integrated-circuit memory array such as an electrically-erasable, electrically-programmable read-only-memory (EEPROM) array. In particular, the invention relates to a method for soft-programming floating-gate memory cells of those arrays.
EEPROMs using hot-carrier-injection programming, as opposed to Fowler-Nordheim tunneling programming, are described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512 K CMOS EEPROM", S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90ns 100 K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787.
When using conventional prior-an, hot-carrier-injection methods for "hard" programming; a reference voltage equal to the substrate voltage (V.sub.SUB, which is perhaps 0 V) is applied to the source of the cell to be programmed; a first positive voltage V.sub.DD, perhaps 6 V to 8 V, is applied to the drain; and a second positive voltage V.sub.P1, perhaps 12 V, is applied to the control gate. Under these conditions, the channel between source and drain is highly conductive, the junction between the drain diffusion and the substrate (channel) is reverse-biased, but the junction between the source diffusion and the substrate is not reverse-biased. Electrons reaching the drain diffusion are subjected to two electric fields, one associated with the reverse-biased drain diffusion junction and the other associated with the positive voltage coupled from the control gate to the floating gate. The electric fields cause electrons (hot carriers) to be injected into the floating gate.
When using conventional methods to erase flash EEPROMs, the drain-column lines are floated (connected to a high impedance), the wordlines are connected to a reference potential, and the source lines are connected to a high positive voltage (approx. +10 V to +15 V). Under these conditions the electric field across the gate oxide region generates a Fowler-Nordheim tunnel current that transfers charge from the floating gate to the source, erasing each memory cell.
One problem associated with prior-art flash EEPROMs has been a wide distribution of threshold voltages after a flash erase operation. The wide distribution is believed to be caused, at least in part, by trapped holes in the gate insulator or by injection of hot holes into the floating gate. Another problem arising in flash EEPROMs is over-erasure of cells. An over-erased cell has a positive charge, causing the channel under the floating gate to be conductive. That over-erased conductive cell short-circuits other cells in its column of parallel-connected cells. One method of compensating for over-erasure is to form the flash EEPROM cells using split gates. Other methods include applying alternating programming and erasing steps as described, for example, in U.S. Pat. No. 5,132,935 issued Jul. 21, 1992, in U.S. Pat. No. 5,122,985 issued Aug. 16, 1992, and references cited in those patents. Both patents relate to compaction, or narrowing, of the threshold voltage distributions of flash erased cells and both patents are assigned to Texas Instruments Incorporated.
It is desirable to have a narrow distribution of positive threshold voltages after performing a flash-erase procedure. In order to obtain the narrow distribution of erased threshold voltages, one flash erase method requires a complete flash-programming step before the actual erase step is performed. Another method requires that light erasing pulses be applied in steps after programming all of the EEPROM cells, checking after each step to see whether or not all of the cells are erased. Yet another method requires that a "soft" flash program step be performed after the erase step to arrive at a final narrow distribution of erased threshold voltages.
Several methods are proposed to narrow or "compact" the distribution of programmed threshold voltages. One of those methods uses wordline stress to cause Fowler-Nordheim injection of electrons into the floating gate. That method is described in "A Novel Erasing Technology for 3.3 V Flash Memory with 64 Mb Capacity and Beyond", Oyama et al., IEDM 1992, (pp. 24.5.1-24.5.4). There is no limit on the magnitude of bitline leakage current using that method. However, the method requires gate voltages higher than the normal programming voltage. Those higher gate voltages require, in turn, special fabrication steps that either lower the electric fields in the dielectric elements or strengthen those dielectric elements.
A second proposed method relies on hot-electron injection into the gate. This method is described in "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", Yamada, et al., IEDM 1991 (pp. 11.4.1-11.1.4). In the second method, the bitlines are biased at a voltage of 6-7 V and the sources are grounded (substrate voltage, or 0 V) while a low voltage (0-2 V) is applied to the control gates. Using this second method, hot holes may be injected into the gate, thus increasing the drain-column-line leakage and defeating the purpose of the compaction.
Recently, methods have been proposed for programming EPROMs using channel-hot electrons with sources biased at a positive voltage with respect to the substrate. Three variations of these methods are described in U.S. Pat. No. 5,218,571 issued Jun. 8, 1993; U.S. Pat. No. 5,295,095 issued Mar. 15, 1994 and U.S. Pat. No. 5,258,949 issued Nov. 2, 1993. In addition, a method for programming EPROMs to increase compaction gate-current efficiency by reverse biasing the source-substrate junctions of the cell or cells being programmed is described in U.S. patent application Ser. No. 08/085,427 filed Oct. 4, 1993 now U.S. Pat. No. 5,467,306 and also assigned to Texas Instruments Incorporated. In that Application, the reverse biasing condition limits the channel currents of individual cells being programmed and of the entire array during a flash-programming compaction step. The control-gate voltages described in that patent application are very low. Because the control-gate voltages are low, the channel currents are low. Therefore, hot-hole injection is essentially eliminated. Minimizing damage to the oxide gate insulators results in an increase in the number of write-erase cycles before cell damage occurs and, therefore, results in an increase in the life of the memory array. However, the time required for the programming operation described in that patent application is relatively long.
While the prior-art includes programming operations for recovering the over-erased cells from depletion and, at the same time, tightening the threshold-voltage distribution without damaging the oxide gate insulators of those cells, the prior-art does not include a method for accomplishing all of those tasks in a manner that permits rapid completion of the programming operation. A rapid programming operation increases the usage efficiency of the memory array in those applications that require numerous read and erase operations.